1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device structured to achieve control of the operation timing of a sense amplifier.
2. Description of the Background Art
A conventional dynamic random access memory is described with regard to a structure of its main portion. It is noted that a signal name having xe2x80x9cZxe2x80x9d at the head represents a signal of active L. Referring to FIG. 13, the conventional semiconductor memory device includes a plurality of memory cells 1, a plurality of word lines WL arranged in the row direction, and a plurality of paired bit lines BL less than i greater than  and ZBL less than i greater than  (i=0, 1, . . . ) arranged in the column direction.
Each bit line pair is connected to a data bus (not shown) via a sense amplifier unit 2. Paired bit lines BL  less than k greater than  and ZBL  less than k greater than  are connected to a sense amplifier unit 2 included in a sense amplifier block SB0 located on the left side with respect to the memory region while paired bit lines BL  less than k+1 greater than  and ZBL  less than k+1 greater than  are connected to a sense amplifier unit 2 included in a sense amplifier block SB1 located on the right side with respect to the memory region (k=0, 2, 4, . . . ).
Referring to FIG. 14, sense amplifier unit 2 includes a sense amplifier SA for detecting a potential difference of a corresponding bit line pair, and an equalizexc2x7precharge circuit EQ for equalizing and precharging a corresponding bit line pair.
Referring again to FIG. 13, sense amplifier SA included in sense amplifier block SB0 is activated by a sense amplifier activation signal SON  less than 0 greater than  and sense amplifier SA included in sense amplifier block SB1 is activated by a sense amplifier activation signal SON  less than 1 greater than .
Equalizexc2x7precharge circuit EQ electrically connects, in response to an equalize signal EQ, a line VBL supplying a reference voltage VBL to a corresponding bit line pair at a predetermined timing.
For writing of data into a memory cell as well as reading of data from a memory cell, a bit line pair is precharged to reference potential VBL in advance.
In the reading operation, externally applied address signals ext.A0 to ext.A12 drive a corresponding word line WL into H level. Data in each memory cell 1 connected to that word line WL is read to cause change in the potential on the bit line. Following this, the sense amplifier activation signal goes to H level. Sense amplifier SA differentially amplifies a potential difference between paired bit lines to define data on the bit line pair as xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d.
As shown in FIG. 15, sense amplifier SA includes PMOS transistors T0 to T2, NMOS transistors T3 to T5, and an inverter I0.
Transistor T0 is connected between a node Vcc receiving a supply voltage and a node Z0 and has its gate receiving an output of inverter I0. Transistor T5 is connected between a node Z1 and a node GND receiving a ground voltage and has its gate receiving sense amplifier activation signal SON. Inverter I0 inverts sense amplifier activation signal SON and outputs the inverted signal.
Transistor T1 is connected between nodes Z0 and Z3 and transistor T3 is connected between nodes Z3 and Z1. Transistor T2 is connected between nodes Z0 and Z4 and transistor T4 is connected between nodes Z4 and Z1. Respective gates of transistors T1 and T3 are connected at node Z4 to bit line BL and respective gates of transistors T2 and T4 are connected at node Z3 to bit line ZBL. When sense amplifier activation signal SON goes H, one of the bit lines is driven to the GND level and the other bit line is driven to the Vcc level according to a potential difference of the bit line pair.
Sense amplifier SA and a control circuit have a relation as described below in conjunction with FIG. 16. Referring to FIG. 16, the conventional semiconductor memory device includes an internal circuit 100 receiving an external row address strobe signal ext.ZRAS to output an internal signal ZSONM, a block selection circuit 102 receiving external address signals ext.A0 to ext.A12 to output block selection signals BS less than 0 greater than  to BS less than 15 greater than , a VBL generating circuit 104 generating reference voltage VBL, a sense amplifier activation signal generating circuit 106 receiving the block selection signals and internal signal ZSONM to output sense amplifier activation signals SON less than 0 greater than  SON less than 15 greater than , and memory array blocks B0, B1, . . . .
A combination of external address signals ext.A0 to ext.A12 causes activation of block selection signals BS less than j greater than  and BS less than j+1 greater than for selecting adjacent memory array blocks Bj and Bj+1 among block selection signals BS less than 0 greater than  to BS less than 15 greater than .
Sense amplifier activation signal generating circuit 106 includes logic circuits 5#0, 5#1, . . . and inverters I1#0, I1#1, . . . arranged respectively corresponding to sense amplifier activation signals SON less than 0 greater than , SON less than 1 greater than , Logic circuit 5#i receives at its inputs internal signal ZSONM and block selection signal BS less than i greater than . Inverter I1#i inverts an output of logic circuit 5#1 to output sense amplifier activation signal SON less than i greater than .
When block selection signal BS less than i greater than  is xe2x80x9cHxe2x80x9d and internal signal ZSONM is xe2x80x9cLxe2x80x9d, sense amplifier activation signal SON less than i greater than  goes xe2x80x9cHxe2x80x9d. Sense amplifier activation signal SON less than I greater than  is supplied to memory array block Bi.
Memory array block Bi includes sense amplifier SA activated by sense amplifier activation signal SON less than i greater than , memory cells holding data to be read by that sense amplifier SA, a plurality of bit line pairs provided corresponding to the memory cells, and equalizexc2x7precharge circuit EQ for equalizing and precharging the bit line pairs.
Memory array block Bk includes paired bit lines BL less than i greater than  and ZBL less than i greater than  as well as sense amplifier block SB0 including sense amplifier unit 2 connected to the paired bit lines BL less than i greater than  and ZBL less than i greater than  in FIG. 13. Memory array block Bk+1 includes paired bit lines BL less than i+1 greater than  and ZBL less than i+1 greater than  as well as sense amplifier block SB1 including sense amplifier unit 2 connected to the paired bit lines BL less than i+1 greater than  and ZBL less than i+1 greater than  in FIG. 13 (k=0, 2, 4, . . . , i=0, 2, 4, . . . ).
All memory array blocks Bi are supplied with reference voltage VBL from VBL generating circuit 104.
An operation of the conventional semiconductor memory device is now described. External row address strobe signal ext.ZRAS goes xe2x80x9cLxe2x80x9d. Address signals which are input at this time cause a specific word line WL to be driven into xe2x80x9cHxe2x80x9d. Data of each memory cell connected to the word line WL is output onto bit line ZBL. Internal signal ZSONM goes xe2x80x9cLxe2x80x9d with a certain delay from the rise timing of word line WL.
It is supposed here that a combination of external input signals ext.A0 to ext.A12 causes block selection signals BS less than 0 greater than  and BS less than 1 greater than for example to become xe2x80x9cHxe2x80x9d.
Signal ZSONM is xe2x80x9cLxe2x80x9d and signals BS less than 0 greater than  and BS less than 1 greater than  are xe2x80x9cHxe2x80x9d. Then, sense amplifier activation signals SON less than 0 greater than  and SON less than 1 greater than  go xe2x80x9cHxe2x80x9d. Sense amplifier activation signals SON less than 0 greater than  and SON less than 1 greater than  at xe2x80x9cHxe2x80x9d activate sense amplifier SA so that data of respective bit lines BL and ZBL are defined as xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d.
The performance of memory cells in such a conventional semiconductor memory device is evaluated through the procedure described below. First, a specific memory cell (object cell) is written with xe2x80x9cLxe2x80x9d data, memory cells adjacent to the object cell and connected to the same word line WL as that to which the object cell is connected are written with xe2x80x9cLxe2x80x9d data, and other memory cells connected to that word line WL are all written with xe2x80x9cHxe2x80x9d data. (This write pattern is herein referred to as a three-sense amplifier pattern.) Then, data of the object cell is read.
It is assumed here that the object cell is connected to paired bit lines BL less than 3 greater than  and ZBL less than 3 greater than . The object cell and memory cells adjacent to the object cell, namely memory cells connected respectively to paired bit lines BL less than 3 greater than  and ZBL less than 3 greater than , BL less than 2 greater than  and ZBL less than 2 greater than , and BL less than 4 greater than  and ZBL less than 4 greater than  are written with xe2x80x9cLxe2x80x9d data. Memory cells connected to paired bit lines BL less than j greater than  and ZBL less than j greater than  (j=0, 1, 5, 6, . . . ) are written with xe2x80x9cHxe2x80x9d data.
Referring to FIG. 17, in a reading operation, xe2x80x9cHxe2x80x9d data is read from most of the memory cells, so that a faster sense amplifier operation is performed for the memory cells storing xe2x80x9cHxe2x80x9d data. On the other hand, a sense amplifier operation for the object cell storing xe2x80x9cLxe2x80x9d data is accordingly delayed.
Floating of ground potential GND which occurs when most of the memory cells are read causes the potential on node GND to float, resulting in a reduced sense margin for reading data of the object cell.
Additionally, bit line ZBL less than 3 greater than  is affected by a coupling noise occurring in reading of data xe2x80x9cHxe2x80x9d from adjacent bit line BL less than 2 greater than , and bit line BL less than 3 greater than  is affected by a coupling noise occurring in reading of data xe2x80x9cLxe2x80x9d from adjacent bit line ZBL less than 4 greater than . The potential difference between paired bit lines BL less than 3 greater than  and ZBL less than 3 greater than  thus decreases which reduces a read margin.
The three-sense amplifier pattern as discussed above can be employed to reduce a read margin for xe2x80x9cLxe2x80x9d data in a specific memory cell by influences of the floating of ground potential GND as well as coupling noises from adjacent bit lines and accordingly accelerate a read failure of xe2x80x9cLxe2x80x9d data. Consequently, products with an enhanced quality can be provided.
However, a test performed following the above-described three-sense amplifier pattern requires that the object cell is changed successively to accomplish data reading and writing for the entire memory cell array. A resultant problem is increase in test time.
An object of the present invention is to provide a semiconductor memory device structured to achieve a fast test for memory cells.
According to one aspect of the present invention, a semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines arranged corresponding to respective rows, and a plurality of bit line pairs arranged corresponding to respective columns, and further includes first sense amplifiers for detecting potential differences of a first plurality of even-numbered bit line pairs among the plurality of bit line pairs, second sense amplifiers for detecting potential differences of a second plurality of odd-numbered bit line pairs among the plurality of bit line pairs, and a sense amplifier control circuit for individually controlling respective operation timings of the first and second sense amplifiers.
Preferably, the sense amplifier control circuit includes a first block control circuit generating a first activation signal for controlling activation of the first sense amplifier, and a second block control circuit generating a second activation signal for controlling activation of the second sense amplifier.
In particular, the first block control circuit includes a delay stage and a circuit for outputting in a normal mode an activation signal as the first activation signal and outputting in a test mode the activation signal delayed by the delay stage as the first activation signal.
In particular, the second block control circuit includes a delay stage and a circuit for outputting in a normal mode an activation signal as the second activation signal and outputting in a test mode the activation signal delayed by the delay stage as the second activation signal.
In particular, the first block control circuit generates the first activation signal in synchronization with an external input signal in a test mode.
In particular, the second block control circuit generates the second activation signal in synchronization with an external input signal in a test mode.
In particular, the first block control circuit generates the first activation signal in synchronization with a first external input signal in a test mode, and the second block control circuit generates the second activation signal in synchronization with a second external input signal in the test mode.
According to another aspect of the invention, a semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, a plurality of word lines arranged corresponding to respective rows, and a plurality of bit line pairs arranged corresponding to respective columns, and further includes first sense amplifiers for detecting potential differences of a first plurality of even-numbered bit line pairs among the plurality of bit line pairs, second sense amplifiers for detecting potential differences of a second plurality of odd-numbered bit line pairs among the plurality of bit line pairs, a first line supplying voltage for precharging the first plurality of even-numbered bit line pairs, a second line supplying voltage for precharging the second plurality of odd-numbered bit line pairs, and a control circuit for individually controlling respective voltages of the first and second lines.
Preferably, the control circuit includes a first block control circuit controlling the voltage of the first line, and a second block control circuit controlling the voltage of the second line.
In particular, the first block control circuit includes a circuit for determining the voltage of the first line according to a signal received from an external input pin in a test mode.
In particular, the second block control circuit includes a circuit for determining the voltage of the second line according to a signal received from an external input pin in a test mode.
In particular, the first block control circuit includes a circuit for determining in a test mode the voltage of the first line based on a first test mode signal according to a signal received from a first external input pin, and the second block control circuit includes a circuit for determining in the test mode the voltage of the second line based on a second test mode signal according to a signal received from a second external input pin.
In particular, the semiconductor memory device further includes a first generating circuit generating a first reference voltage, and a second generating circuit generating a second reference voltage different from the first reference voltage. The first block control circuit supplies the first reference voltage to the first line in a normal mode, and supplies the second reference voltage to the first line in a test mode. The second block control circuit supplies the first reference voltage to the second line in a normal mode, and supplies the second reference voltage to the second line in a test mode.
The semiconductor memory device according to the present invention can thus individually control respective activation timings of sense amplifiers connected to even-numbered bit line pairs and sense amplifiers connected to odd-numbered bit line pairs. Then, any defective memory cell can speedily be detected without manipulation of data writing pattern.
Further, as the semiconductor memory device according to the invention includes the delay stage in the sense amplifier control circuit, the activation timing can be delayed.
Additionally, the semiconductor memory device according to the invention can activate a sense amplifier in synchronization with an external input.
Further, the semiconductor memory device according to the invention can individually control respective potentials of a line precharging even-numbered bit line pairs and a line precharging odd-numbered bit line pairs. Then, a high-speed detection of any defective memory cell is possible without manipulation of data writing pattern.
Particularly, the semiconductor memory device according to the invention can determine respective potentials of lines by means of external input. In addition, the semiconductor memory device according to the invention includes circuits for generating a plurality of potentials to enable control of the potential of each line.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.